Summary of information related to WP9

In this Work Package, important parts of the EISCAT_3D radar transmitter subsystem will be designed and evaluated. These particular areas of the transmitter design were planned to be addressed already during the FP6 Design Study but was unfortunately left unfinished due to lack of manpower and time.

This Work Package will contain the following activities:

  • Design, prototyping and testing of the system for the generation and modulation of the low-level RF drive signals.
  • Prototyping and testing of the beam-forming of the transmitted beam.
  • Testing of the design of the transmit-receive (T/R) switching and receiver protection, particularly when operating with the power amplifier system that was developed in the FP6 Design Study.
  • Design and test specification of power amplifier stage for the transmitter, with particular considerations also to power efficiency.

The main work in this Work Package will be performed by the Swedish Institute of Space Physics, while interacting with EISCAT Scientific Association and Luleå Technical University.

Deliverables

Deliverable 9.1: Report on the design of the digital exciter

January 20, 2012
Deliverable 9.1 of the FP7-supported EISCAT_3D Preparatory Phase project is a report describing the design, construction and verification of a prototype transmitter exciter for the EISCAT_3D phased-array research radar system.

The two prototype versions of the exciter presented here are designed around the Analog Devices AD9957 quadrature upconverter (QDUC) evaluation board, EVAL-AD9957. The second (triple-channel) version can implement the required transmitter arbitrary modulation, spectrum masking and time-domain beam steering capabilities up to baseband data rates of at least 60 Msamples/second, while at the same time maintaining phase noise and spurious emission levels below the EISCAT_3D performance specification limits. It is recommended as a suitable starting point for the design of a mass-produced, multi-channel arbitrary-waveform exciter for the EISCAT_3D radar.

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Shown above are the most important subsystems of the prototype single-channel AD9957-based exciter. The PROM is programmed with eight equal-magnitude I/Q pairs, positioned at (n · π/4, n = 0,…,7) on the unit circle; this data set can be used to implement constant-amplitude eight-phase coding at many existing ISR systems.

Deliverable 9.2: Technical report on the T/R switch design

April 15, 2013
Task 9.3 of the EISCAT_3D Preparatory Phase is concerned with the verification and evaluation of the transmitter/receiver switch design.

Deliverable 9.2 is a report covering the design and testing of a T/R switch realised on microstripline technology. The tested switch mainly meets the deign goals for use in the EISCAT_3D system. As designed, the prototype T/R switch meets the power handling and switching time design targets. It also approaches the isolation and loss targets to within acceptable tolerances, considering the intended application:

  • At 350 W incident power, only -20 dBm leaks through to the receiver; this is about 10 dB less than the level that low noise HEMTs can withstand indefinitely without degradation
  • With a sky temperature exceeding 200 K and a receiver noise temperature of more than 35 K, an extra 15 K noise temperature added by the T/R switch (36 K instead of 21 K) translates to a signal-noise ratio loss of less than 6 %.

Addendum: When this Deliverable was originally reported, the high power tests of the T/R switches had failed since the used PIN-diodes did not withstand the required power. The design criteria parameters presented in the Deliverable confirmed that the operating conditions for the PIN-diodes with some margin were within those presented in the data sheets issued by the manufacturer (MA/Com). Contact with MA/Com was established, and another PIN-diode version was put into the case type that fitted our design (the new version was originally not available in the “micro strip” case we had selected). The conclusion after the 1000 hours continuous test is that the design works according to the design specifications and targets as given in the baseline documents.

Deliverable 9.3: Report containing the conclusions from the beam-steering tests

April 15, 2013
As part of the Work Package 9 activities in EISCAT_3D Preparatory Phase, on-the-air tests of the IRF-developed triple channel arbitrary-waveform exciter prototype were carried out at the Jicamarca Radio Observatory (JRO) in Peru from March 19, 2012 to March 24, 2012 inclusive. The IRF staff involved were Dr. Gudmund Wannberg, IRF-K (now ℅ Wannberg Radarkonsult AB) and Mr. Walter Puccio, IRF-U.

The purpose of these tests was threefold:

  1. to verify that the IRF-developed exciter prototype could successfully drive a high-power incoherent-scatter radar at its output frequency without running into RF feedback problems
  2. to verify the ability of the exciter to generate phase-stable
    carrier signals modulated by completely arbitrary waveforms
  3. to verify the beam-steering capabilities of the triple-channel prototype at least in principle through on-the-air tests.
    Deliverable 9.3 is a report focusing on the beam-steering tests.

The conclusions from the tests are that technically these tests at JRO must be characterized as a total success:

  1. the ability of an AD9957-based exciter to drive a 2 MW, 50-MHz transmitter at the output frequency without developing feedback problems has been demonstrated
  2. using long Chu codes, which cycle the real and imaginary halves of the baseband data word through their entire amplitude ranges, the arbitrary-waveform capability of the AD9957 is verified at baseband rates up to 15 Mwords (complex) per second

the FP6 Design Study proposal for EISCAT_3D transmit beam-steering, i.e. to control individual array elements by numerically phase-shifting independent exciters, is demonstrated and validated in principle.

Deliverable 9.4: Report with design specification of power amplifiers

April 8, 2013
Note: This Deliverable was not part of the original Work Plan.

One transmitter design for EISCAT_3D was tested during the FP6 Design Study. It was found that this design needed some improvements, primarily for energy efficiency but also to enable industrial production of the transmitter units. Hence, Task 9.4 of the EISCAT_3D Preparatory Phase involves specifying the design of the power amplifier to be used in the EISCAT_3D radar system. Deliverable 9.4 includes these design specifications.

Milestones

Milestone 9.1: First exciter prototype in operation

March 1, 2012
As part of this Work Package, a single-channel exciter comprising AD9957 evaluation board, a broadband MMIC RF amplifier and a command interface has been designed and prototyped. The interface contains a baseband data PROM, programmed with a set of I/Q data defining eight points on the periphery of the unit circle ([0,…,7]×45°) which can be selected at will by external command. The prototype has been debugged and verified by using three bits from the EISCAT Radar Controller to control the PROM, feeding the resulting analog output signal at ≈108 MHz into the first i.f. of the Kiruna EISCAT UHF receiver and sampling and displaying the signal using a special purpose experiment running under EROS.

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The output signal is phase-stable to better than one part in 10¹¹ over 5 seconds; the phase progression when stepping through the eight possible phases is repeatable to within the resolution of the measurement system over the same time period. The first operation of this prototype exciter constitutes Milestone 9.1.

This Milestone was reached in May 2011.

Milestone 9.2: Revision of the exciter design finalised

March 1, 2012
A fully digital exciter design based on an off-the-shelf digital up-converter chip is developed as part of this Work Package. An initial prototype was produced and in operation (Milestone 9.1) in May 2011. The second prototype is a triple channel exciter, comprising three synchronised AD9957 QDUCs running off a common clock and being modulated by individually preprocessed baseband data streams from an FPGA controller. The revision of the design of the prototype exciter is Milestone 9.2.

This Milestone was reached in September 2011.

Milestone 9.3: Two additional exciter units, using the revised design delivered

April 10, 2013
In the original Work Plan for Work Package 9 of the EISCAT_3D Preparatory Phase, an exciter design would be tested by connecting three exciter units to a stable timing system and a control computer. However, it was found to be more convenient to use one exciter unit with three channels instead. Details of the exciter can be found in Deliverable 9.1.

The triple-channel exciter unit comprises Milestone 9.3. This Milestone was reached in January 2012.

Milestone 9.4: First operation of beam-steering capabilities demonstrated

April 9, 2013
As part of the EISCAT_3D Work Package 9, tests of the IRF-developed triple channel arbitrary-waveform exciter prototype were carried out at the Jicamarca Radio Observatory (JRO) in Peru from March 19, 2012 to March 24, 2012. One of the purposes of these tests was to verify the beam-steering capabilities of the triple-channel prototype.

The techniques and configurations used at JRO deviate in several respects from the Work Plan of Task 9.2 in the EISCAT_3D Preparatory Phase. Instead of the planned use of time-delay-based beam-steering and beam tapering with three exciter units, direct phase steering with two exciter channels and no amplitude tapering was utilised. These deviations were due to the setup of the JRO system.

The proposed beam-steering, to control individual array elements by numerically phase-shifting independent exciters, was demonstrated and validated.

The successful demonstration of the beam-steering capabilities corresponds to Milestone 9.4 of the EISCAT_3D Preparatory Phase. This Milestone was reached in March 2012.

Milestone 9.5: Evaluation of T/R switch prototypes completed

April 9, 2013
Task 9.3 of the EISCAT_3D Preparatory Phase is concerned with verification and evaluation of the transmitter/receiver switch design.

This T/R-switch was realised on microstripline technology, which simplifies the integration in a modular system with a combined Transmit/Receive module.

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As designed, the prototype T/R switch meets the power handling and switching time design targets. It also approaches the isolation and loss targets to within acceptable tolerances, considering the
intended application:

  • At 350 W incident power, only -20 dBm leaks through to the receiver; this is about 10 dB less than the level that low noise HEMTs can withstand indefinitely without degradation.
  • With a sky temperature exceeding 200 K and a receiver noise temperature of > 35 K, an extra 15 K noise temperature added by the T/R switch (36 K instead of 21 K) translates to a S/N loss of less than 6 %.

However, when the tests were started in the beginning of January, PIN-diode D1 in two different prototype T/R switches failed, even though the thermal load on these was estimated to be far below the specified maximum. The manufacturer admitted that the bonding strips connecting the diode chips to the external microstrip tabs were underrated and probably fusing under the RF current load. The factory promised to ship some improved engineering samples of the
diode, with larger bonding strips, for further tests.

The completed evaluation of the T/R switch prototypes is Milestone 9.5 of the project. This Milestone was reached in February 2013.

Attachements

Documents related to WP9 can be found in our external library.

Related documents